Integer power arithmetic is often required in data processing systems. Commonly, the execution of the integer power function is accomplished by using the existing arithmetic circuitry that traditionally just performs additions and subtractions. In these traditional arithmetic functional units, algorithms are performed in software to perform a multiplication operation by performing a series of additions. Multiple multiplication operations are performed to execute the integer power function. More recent data processing systems include special purpose arithmetic units. Some special purpose arithmetic units include multiplier circuitry. Integer power functions are accomplished with the multiplier circuit by repetitively multiplying a base number itself in accordance with the exponent.
However, recent systems have included circuitry especially dedicated to performing integer power functions. SU 1179327 (Abstract only available) entitled, "Digital Data-Processing Exponential Function Generator has Computing Unit Outputs From Base and Exponent Registers to AND-GATES and OR-GATES With Output-to-Output Multipliers", discloses an exponential functional circuit where the exponent, in binary form, controls multiplication of the base.
SU 1246092 (Abstract only available) entitled, "Digital Computing Powering APPTS has Exponent Coder Controlling Passage of Conjunctions From Argument Digital Product Coders to Output Adder", discloses an arithmetic circuit include an adder and a multiplier.
IBM Technical Disclosure Bulletin Vol. 14, No. 1, June, 1971, pp. 328-330, entitled "Efficient Arithmetic Apparatus and Method", discloses an arithmetic circuit that performs exponential logarithmic quotient and square root functions.
IBM Technical Disclosure Bulletin, Vol. 25, No. 1, June, 1982 pp. 171-173, entitled "Exponential by Sequential Squaring", discloses an algorithm for performing exponential operations.
U.S. Pat. No. 4,225,933 to Monden filed Nov. 16, 1978 and issued Sep. 30, 1980, entitled "Exponential Function Computing Apparatus", discloses a data shifting and adding circuit to perform exponential functions.
U.S. Pat. No. 4,229,801 to Whipple, filed Dec. 11, 1978 and issued Oct. 21, 1980, entitled "Floating Point Processor Having Concurrent Exponent/Mantissa Operation", discloses an arithmetic unit that performs exponent/sign related calculations concurrently with mantissa related operations in floating point arithmetic.
U.S. Pat. No. 4,410,956 to Yoshida, filed Mar. 30, 1981 and issued Oct. 18, 1983, entitled "Exponential Operation Device", discloses an exponential arithmetic circuit that determines whether the base parameter is positive or negative and whether the exponential parameter is an integer.
U.S. Pat. No. 4,758,975 to Omoda et al. filed Dec. 11, 1985 and issued Jul. 19, 1988, entitled "Data Processor Capable of Processing Floating Point Data With Exponent Part of Fixed or Variable Length", discloses a data processor with a latch for latching in a floating point register floating point exponent data.
DE 3931545 entitled, "Floating Point Processor--has Adder Subtracter Handling Exponent Part for Improved Execution of Multiplication and Division", provides circuitry to perform multiplication and division in addition to addition and subtraction.
IBM Technical Disclosure Bulletin Vol. 32 No. 7, December, 1989, pp. 222-223, entitled "16-Bit Floating-Point Math in an 8-Bit Microprocessor", discloses a program that performs a 16-bit floating point mathematical operation with a signed 8-bit exponent in an 8-bit microprocessor.
IBM Technical Disclosure Bulletin, Vol. 33, No. 1B, June, 1990. pp. 312-313, entitled "Exponent Shift Count Logic" discloses a circuit for performing exponent operations including an adder and shifter.
The object of the present invention is to provide an exponent circuit to quickly perform integer power operations.